Design and Implementation of Efficient Carry Select Adder on Reconfigurable Device Using Novel Logic Formulation

Abstract

Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. The logic operations involved in conventional carry select adder (CSLA) and binary to excess-1 converter (BEC)-based CSLA are data dependence and redundant logic operations. In this paper, proposed a new logic formulation for CSLA to eliminate the redundant logic operations present in the conventional CSLA. In the proposed scheme, the carry select (CS) operation is scheduled before the calculation of final-sum, which is different from the conventional approach. The proposed CSLA design has reduced area and delay as compared with BEC-based CSLA. Due to the small carry-output delay, the proposed CSLA design is suitable for Multistage CSLA(SQRT-CSLA).The performance of the CSLA is evaluated by implementing a MAC unit using either conventional, BEC or proposed CSLA in the adder part, for different bit-widths. This work focuses on the performance of CSLA in terms of area, delay and power. The analysis of the result shows that the MAC unit using proposed SQRT-CSLA has less area, delay and power when compared with MAC unit with existing SQRT-CSLAs. The system has been designed efficiently using Verilog HDL codes and simulated using Quartus II 9.1.The hardware implementation is done by using Altera-FPGA.