Concording Two FPGAS for Low Power Consumption

Abstract

— In the era of electronic design, SOC technology is the recent developing technology. In order to increase the efficiency of the system and reducing the power consumption, we are in need of realizing the whole system function in a single or a very few chips. Universal Asynchronous Receiver Transmitter (UART) is a kind of serial communication protocol. In parallel communication the cost as well as complexity of the system increases due to simultaneous transmission of data bits on multiple wires. Serial communication alleviates this drawback of parallel communication and emerges effectively in many applications for long distance communication as it reduces the signal distortion because of its simple structure. Specifically, we focuses on their effective data transmission rates and ratios. The usage of FPGA systems in real time domain is  a very fruitful assertion as the FPGA devices are coming with processing cores for Real Time data processing. As FPGA performance and capabilities are developing substantially in recent years, FPGA-based designs are employed to implement complex functionalities and designs. To make this possible we have to establish a real time data communication between two FPGA devices. UART includes three kernel modules which are the baud rate generator, Receiver and Transmitter. The UART implemented with VHDL language can be integrated into the FPGA to achieve Condense, firm and reliable data transmission which will be an mandatory criteria to build a complex data asset system. Hence, this Paper focusses on the establishment of  a real time data communication between Two FPGA’s with the help of a reconfigurable baud rate generator and a sensor attached to the ADC which will provide the data which needs to be communicated to the PC through which FPGAs can talk to each other effectively and results in low power consumption