Design of BCH Decoder Based On Multi-bit Error Correction Codes Using VHDL

Abstract

Error-correction codes are the codes used to correct the errors occurred during the transmission of the data in the undependable communication mediums. The idea behind these codes is to add redundancy bits to the data being transmitted so that even if errors occur due to noise in the channel, the data can be correctly received at the destination end point. Bose, Ray- Chaudhuri, Hocquenghem (BCH) codes are one of the error-correcting codes. Error detection is the detection of errors caused by the noise or other impairments during transmission from the transmitter to the receiver. It uses the concept of redundancy, which means adding of extra bits for detecting errors at the destination. In error correction the receiver can use any of the error-correcting code, which can automatically corrects certain errors and enables reconstruction of the original data. These can be done by means of digital filters by providing amount of delay for processing error detection and correction respectively. Over the duration, lots of techniques that make use of the filters structure and its properties to achieve fault tolerance have been proposed. Enhancing technology makes system more complex that include many filters. In those complex systems, it is frequent to have number of filters in circuit that functions in parallel architecture. In parallel combination of filters there apply the same filter to different input signals. So, from this case study the idea to implement parallel filters and digitally correct the errors are generalized. It has been proposed to protect digital signal processing circuits by using ECC i.e. Bose, Ray- Chaudhari, Hocquenghem (BCH) codes. The technique has evaluated using study on parallel infinite impulse response filters making effectiveness in terms of protection and implementation cost. The enhanced BCH decoder is designed using hardware description language called Verilog and synthesized in Xilinx ISE Tools 13.2.